A 1.5 V 2 GS/s 82.1 dB-SFDR Track and Hold Circuit Based on the Time-Divided Post-Distortion Cancelation Technique
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DOI: 10.1109/tcsii.2022.3204031
Abstract: This brief presents a track and hold (T/H) circuit for time-interleaved analog-to-digital converters based on a new linearization technique—time-divided post-distortion cancellation. Fabricated in 65 nm CMOS, it achieves 82.1 dB SFDR with a 700-mV near-Nyquist… read more here.
Keywords: time divided; time; track hold; circuit ... See more keywords