LAUSR

The recently proposed semi‐floating gate memory technology shows the potential to balance conflicts between writing speed and data storage. Although the introduction of the p–n junction greatly improves device writing speed, the inevitable junction leakage limits the further extension of data retention time. A local nonvolatile electric field is introduced by exploiting the polarization of ferroelectric gate dielectric HfZrO4 to modulate the charge leakage speed of the p–n junction since the carrier density of 2D materials can be efficiently regulated. The refresh time is greatly prolonged more than 535%, solving the bottleneck problem of relatively short retention time of previous semi‐floating gate memory. In addition, the characteristics of device under low operation voltage is also explored, which can serve for further power reducing. This design realizes the combination of ultrafast writing operation and significant enhanced data retention ability, which provides a new idea of the development for high speed non‐volatile memory technology.