LAUSR

Organic thin-film transistors (TFTs) are promising devices to be employed in future flexible, large-area electronics applications, such as active-matrix displays and sensor arrays.[1–3] The possibility to deposit organic semiconductors at relatively low temperatures makes it possible to fabricate organic TFTs on unconventional substrate materials, such as glass,[4,5] plastic foils,[6–8] textiles,[9] or paper.[10,11] The use of these substrate materials offers opportunities for a variety of novel applications, but they are usually characterized by a larger surface roughness than conventional substrate materials, and this can have detrimental effects on the performance of the devices.[12–26] In this work we study the impact of the surface roughness of the gate dielectric on the electrical performance of bottom-gate organic TFTs. As model organic semiconductor, we employ the small-molecule semiconductor dinaphtho[2,3-b:2',3'-f ]thieno[3,2-b]thiophene (DNTT[27]), since its unique combination of electrical performance and long-term stability makes it ideally suited for this investigation.[28–31] Since the current–voltage characteristics of organic TFTs depend on various parameters other than the surface roughness,[32,33] it is important that the only parameter we vary in our experiments is the surface roughness, as simultaneous changes in other parameters might obscure the effect we intend to investigate. All TFTs were thus fabricated using the same materials, the same layer thicknesses, and the same process conditions, with one exception, namely the substrate temperature during the deposition of the aluminum gate electrodes (in order to analyze the impact of the surface roughness) or the substrate temperature during the deposition of the organic semiconducting layer (in order to disentangle the relations between the surface roughness of the gate dielectric, the grain density of the semiconductor layer, and the density of trap states in the organic-semiconductor layer). By varying the substrate temperature during the aluminum deposition we are able to tune the surface roughness of the gate electrode and thereby the surface roughness of the gate dielectric over approximately one order of magnitude without having to change any other process parameters, so that any differences observed in the TFT In organic thin-film transistors (TFTs) fabricated in the inverted (bottom-gate) device structure, the surface roughness of the gate dielectric onto which the organic-semiconductor layer is deposited is expected to have a significant effect on the TFT characteristics. To quantitatively evaluate this effect, a method to tune the surface roughness of a gate dielectric consisting of a thin layer of aluminum oxide and an alkylphosphonic acid self-assembled monolayer over a wide range by controlling a single process parameter, namely the substrate temperature during the deposition of the aluminum gate electrodes, is developed. All other process parameters remain constant in the experiments, so that any differences observed in the TFT performance can be confidently ascribed to effects related to the difference in the gate-dielectric surface roughness. It is found that an increase in surface roughness leads to a significant decrease in the effective charge-carrier mobility and an increase in the subthreshold swing. It is shown that a larger gate-dielectric surface roughness leads to a larger density of grain boundaries in the semiconductor layer, which in turn produces a larger density of localized trap states in the semiconductor.