LAUSR

The fundamental logic states of 1 and 0 in Complementary Metal-Oxide-Semiconductor (CMOS) are essential for modern high-speed non-volatile solid-state memories. However, the accumulated storage signal in conventional physical components often leads to data distortion after multiple write operations. This necessitates a write-verify operation to ensure proper values within the 0/1 threshold ranges. In this work, a non-gradual switching memory with two distinct stable resistance levels is introduced, enabled by the asymmetric vertical structure of monolayer vacancy-induced oxidized Ti3C2Tx MXene for efficient carrier trapping and releasing. This non-cumulative resistance effect allows non-volatile memories to attain valid 0/1 logic levels through direct reprogramming, eliminating the need for a write-verify operation. The device exhibits superior performance characteristics, including short write/erase times (100 ns), a large switching ratio (≈3 × 104), long cyclic endurance (>104 cycles), extended retention (>4 × 106 s), and highly resistive stability (>104 continuous write operations). These findings present promising avenues for next-generation resistive memories, offering faster programming speed, exceptional write performance, and streamlined algorithms.