LAUSR

As the VLSI technology is heading toward deep subnanometer range, the NBTI effect has emerged as a major reliability issue for the state-of-the-art CMOS as well as FinFET-based circuits. NBTI causes an incremental deviation in the threshold voltage of PMOS and hence causes variation in timing of digital circuits. Further, NBTI may increase the delay of circuits which are lying in the critical path of a system. This timing mismatch is a serious concern for synchronous clock-based circuits such as dynamic logic gates employed in a register file which itself lies in the critical path of a microprocessor. This is a critical reliability issue for microprocessors and microcontrollers which are used in electronic systems with high lifetime such as sensors. This paper has introduced a reliable FinFET-based low-power 32-word $$\times $$× 32-bit register file which is designed using 32-nm BSIM-IMG technology. In this paper, the impact of NBTI on the different modules of FinFET-based register file has been studied. This analysis reveals that the domino OR gate bit-line is responsible for much of the NBTI degradation in a register file. Hence, a novel aging-aware domino bit-line has been proposed here which is capable of maintaining a constant performance under NBTI degradation. This proposed domino bit-line is further used to design a novel register file which is capable of maintaining a constant performance for a lifetime of more than 10 years.