LAUSR

In this paper, two methods for fine-tuning the accuracy of bias-estimation with conditional probability of the bottom signed bit (BSB) for fixed-width two’s complement modified Booth multiplier are proposed. We calculate the conditional probability between the BSB and partial product elements including other signed bits to estimate the expected value of truncation part. This makes fine-tuning of accuracy instead of column-wise coarse-tuning in fixed-width multipliers possible. We propose two methods based on the BSB to estimate and compensate the fixed-width multiplier for minimization of truncation error. Two proposed methods can improve the signal-to-noise (SNR) with a small area penalty in fixed-width multiplier. Statistics on the SNR were analyzed, and the hardware performance results validate the effectiveness of the proposed methods. In real-world implementation, compared with the discrete cosine transform (DCT) core using direct-truncated (D-T) multipliers, the DCT cores using the proposed BSB_AE and BSB_HC multipliers increase average peak signal-to-noise ratio (PSNR) by 27 and 31% with only a 6 and 7% area penalty, respectively.