LAUSR

Network on chip is widely restricted with power utilization and area occupation due to the usage of buffers. Hence, the design of bufferless architecture entirely eliminates such kind of limitations. However, conventional methodologies will not provide low-power design with enhanced features by means of operational frequency and area. This work introduces an optimization algorithm along with bufferless routing in chip design. Ant lion optimized (ALO) routing topology in bufferless router achieves very less power. Power dissipation of ALO-bufferless technique is evaluated with conventional topologies, such as spin, octagon and cliché. Xilinx ISE design suite 14.5 is used for the purpose of design and validation of the planned work, and it is compared with fault-tolerant deflection routing and hierarchical FTDR in terms of throughput and fault rate. ALO-based bufferless routing achieves operational frequency of 780.153 MHz with 0.413 mW power consumption; while ant lion optimized buffered routing achieves operational frequency of 426.995 MHz and 0.750 mW for speed and power, respectively.