LAUSR

This paper focuses on the study of a compact tem-perature-compensated CMOS voltage reference (VR) with high reliability. The temperature coefficient (TC) of the gate-source voltage for a subthreshold NMOSFET has been derived and utilized to perform effective temperature compensation with a proportional to absolute temperature (PTAT) drain current. The desirable PTAT current is provided with reliable power supply rejection ratio (PSRR) based on low-voltage self-biased cascode subthrehold operation with enhanced negative feedback. The resulting reference voltage is less sensitive to the process variations of on-chip resistors and absolute currents as well as the TC and PSRR. In addition, the impact of the gate-source voltage variation is alleviated, thus ensuring high reliability of the proposed VR. The measurement results without trimming in 40-nm CMOS process demonstrate that the average of TC is 5.1 and 19.1 $$\hbox {ppm}/^\circ \hbox {C}$$ppm/∘C in the temperature range of −20 to −80 $$^\circ \hbox {C}$$∘C and −40 to −120 $$^\circ \hbox {C}$$∘C, respectively, and the worst PSRR of −55.0 dB at 300 kHz is achieved, while the line regulation is better than 0.32 mV/V in the supply range of 0.9–1.6 V. The average current consumption is 8.9 $$\upmu \hbox {A}$$μA at 0.7-V supply, with a die area of only 0.006 $$\hbox {mm}^2$$mm2.