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Ultra-low-power capacitor-splitting switching algorithm with minus energy for SAR ADCs

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In this letter, an ultra-low-power capacitor-splitting switching algorithm for successive approximation register analog-to-digital converters is proposed. To achieve low power, the first three bit cycles consume no power from the… Click to show full abstract

In this letter, an ultra-low-power capacitor-splitting switching algorithm for successive approximation register analog-to-digital converters is proposed. To achieve low power, the first three bit cycles consume no power from the reference by introducing minus energy during the third bit cycle and proper switching algorithm. To further reduce the switching energy, only single-side capacitors are switched from the forth bit cycle. Besides, to add one bit, the dummy capacitor is realized by four unit capacitors and switched to generate the least significant bit. Compared to the Sanyal and Sun switching technique, the proposed capacitor switching method achieves 94.19% energy saving and 47.66% capacitor area reduction.

Keywords: energy; capacitor; bit; power; switching algorithm; low power

Journal Title: Analog Integrated Circuits and Signal Processing
Year Published: 2017

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