LAUSR

This paper presents a novel time-to-digital converter (TDC) based on sliding scale technique (SST) for effectively improving the conversion linearity. The architecture adopts multi-segment conversion scheme including a coarse counter and a couple of two-stage interpolators. The time resolution is stabilized against process, voltage and temperature variations by delay-locked loop control. Besides, since the nonlinearity of the two-stage fine-interpolated structure is free from accumulating with the input time, the restriction on the range extension is effectively released. The proposed hybrid TDC fabricated by GSMC 0.18 µm CMOS process with 1.8 V supply voltage is suitable for random time-of-flight measurement. Based on SST and average method, the experiment results show that the time resolution and the maximum dynamic range can be reached to 250 ps and 4 µs. The DNL and INL are distributed in − 0.26 to 0.30 LSB and − 0.42 to 0.46 LSB respectively, and the single shot precision is 0.91 LSB.