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This letter presents a harmonic-mode PLL (H-PLL) that avoids additional multiplication, filtering, and amplification stages and thus results in an area-efficient implementation. A proof-of-concept 57.5-mW 65-nm CMOS PLL prototype operating… Click to show full abstract
This letter presents a harmonic-mode PLL (H-PLL) that avoids additional multiplication, filtering, and amplification stages and thus results in an area-efficient implementation. A proof-of-concept 57.5-mW 65-nm CMOS PLL prototype operating at 171 GHz provides − 14.2 dBm output power and a spur level of − 67.5 dBc. The PLL is built with a varactor-free 2fO VCO, which is tuned by varying transistor intrinsic capacitances via MOS bulk voltages.
Keywords:
mode pll;
pll;
harmonic mode;
dbm output;
output power;
171 ghz
Journal Title: Analog Integrated Circuits and Signal Processing
Year Published: 2019
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Journal Title: Analog Integrated Circuits and Signal Processing
Year Published: 2019
Link to full text (if available)
Share on Social Media: Sign Up to like & get
recommendations!