LAUSR

A 1-V 3rd-order 1-bit discrete time (DT) Σ-Δ modulator is designed and implemented in a 40-nm CMOS technology. With the input feed forward coefficient optimized, the output swings of the integrators are minimized. The bootstrapped switches are utilized at the input of the modulator to improve the linearity of the sampled signal. In order to reduce the power consumption in low voltage environment, the inverter-based static–dynamic hybrid structure amplifier is proposed and a dynamic comparator is employed. The designed modulator achieves 89.8 dB maximum SNR and 84.1 dB maximum SNDR over a 100 kHz signal bandwidth with a sampling frequency of 25.6 MHz, and the dynamic range (DR) is 86.7 dB. The proposed modulator shows competitive figure of merits (FOMs) compared with other near-1V-supply hundred-kHz-BW modulators.