LAUSR

This paper covers the design, characterization and calibration of stress sensors useful to measure the in-plane stress at the surface of integrated circuits. Each sensor is based on piezo-FET current mirrors aligned in four different directions; the mismatch in the current output in each mirror is related to the stress aligned with the device, then, the changes in the output currents can be used to estimate both the magnitude and direction of uniaxial stress along the active area. The piezoFETs in the sensors are the same NMOS and PMOS transistors available in the IC technology, thus the device can be integrated into any CMOS process. Each kind of transistor has its sensitivity enhanced by a different component of the stress; the PMOS sensor reacts to the shear stress while the NMOS is sensitive to longitudinal stress. Compared with previous stress sensor designs based in piezoresistors, by using both PMOS and NMOS, it is possible to improve the estimation of the in-plane stress and isolate all the stress components. Symmetry and common-centroid are used in the layout to improve the match in the mirror; as a result, the design of a compact octagonal device is presented. The special layout and circuit design also allow canceling out out-of-plane components of the stress and other common-mode effects. Each sensor requires 40 × 60 µm 2 total area and was fabricated using 0.6 µm CMOS technology. Samples of the devices were tested using a four-point bending test configuration to apply uniaxial stress. The experimental results show a linear relationship of the output current with the stress, which are in accordance with the piezoresistive effect theory. Using the differential output currents of both PMOS and NMOS piezo-FET current mirrors, it is possible to estimate the uniaxial stress magnitude and direction with an angle error lower than 4°. These kinds of piezoFET devices are suitable to determine the stress state in a local area, and several of them can be placed together in a stress-sensor matrix to map the stress on ICs.