LAUSR

The next generation of non-volatile memory elements have been attracting significant attention for future emerging memory applications in recent years. Several technologies have been developed to occupy a new field in storage-class memory and even replace NAND flash memories in sequential logic applications, due to their advantageous features such as fast programming time, low power consumption, high endurance and retention. Latch topologies have been proposed to implement these new technologies. In this article, we present new non-volatile Latch topology. We focus on a D Latch topology that uses memristors as memory elements combined with CMOS components. The memristor device has been implemented using an accurate Verilog-A model exploring the experimental data of a real OxRRAM device. Our simulation results explore low-voltage and reliable non-volatile Latch designs. Indeed, we integrate this Latch design to behave as a counter application using both binary and Gray codes. Moreover, this topology has been compared with other non-volatile topologies in terms of power consumption, cell size, energy, programing time and robustness at different programming voltage values. We proved that the memristor-based Latch has non-volatile characteristics and is able to store data.