LAUSR

An improved theoretical model for metal–ferroelectric–metal–insulator–semiconductor field-effect transistors (MFMIS FETs) is presented. The basic theory describing the ferroelectric behavior is replaced by the dipole switching theory (DST) because of its deeper physical meaning and its ability to account for the history-dependent electric field effect of the ferroelectric. Using the combination of DST and the theory of series capacitances, the capacitance–voltage (C–V) characteristic of the MFMIS structure is simulated, while the combination of the DST with Pao and Sah’s double integral enables the simulation of the drain current–gate voltage (ID–VGS) and drain current–drain voltage (ID–VDS) characteristics. The good agreement between the simulation and experimental results confirms the validity of this model. The effects of the area ratio AF/AM on the C–V, ID–VGS, and ID–VDS characteristics are further provided by the model. The simulation results indicate that the applied voltage and ID ON/OFF ratio decrease while the memory window widens as the area-ratio increases. This work is expected to help direct the design and fabrication of MFMIS-based devices.