LAUSR

Memristive crossbar arrays are believed to be the future of high-density nonvolatile memory and neuromorphic systems. However, significant challenges related to the passive crossbar architecture, for example, the sneak current issue, impose limitations on their performance. One of the well-known ways to overcome this problem is to use a one-transistor one-memristor (1T1M) scheme. Nevertheless, for a sufficiently large crossbar, even with a 1T1M architecture, problems appear not only with sneak currents but also with leakage through the gates of the transistors and the discharge of their capacitances. These effects are analyzed herein by simulations and analytically to determine their influence on the performance of a 1T1M crossbar, depending on its dimensions. Numerical results are presented for the examples of $$\mathrm{(CoFeB)}_x(\mathrm{LiNbO}_3)_{100-x}$$ ( CoFeB ) x ( LiNbO 3 ) 100 - x nanocomposite and $$\mathrm{ZrO}_2$$ ZrO 2 (Y)-based memristive structures. The results reveal that the sneak, discharge, and (to a lesser extent) leakage currents can severely degrade the performance of even a not very large ( $$<\,10^3\times 10^3$$ < 10 3 × 10 3 ) 1T1M crossbar. Finally, analytical estimates are used to reveal how a well-known, simple special scheme for switching and reading can fix these negative effects, even for a 1T1M memristive crossbar with rather large dimensions ( $$\sim \,10^6\times 10^6$$ ∼ 10 6 × 10 6 ), taking into account its plausible geometrical size and the scaling dependence of its constituent elements.