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Fabrication of Planar-Integrated SIS Mixer Circuits with Improved Uniformity and Yield

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Single-pixel prototype superconductor–insulator–superconductor (SIS) mixer integrated circuits (ICs) for multi-beam heterodyne receivers were fabricated. We introduced plasma-enhanced chemical vapor deposition (PE-CVD) for insulator layer deposition and machine-aligned via-hole etching for… Click to show full abstract

Single-pixel prototype superconductor–insulator–superconductor (SIS) mixer integrated circuits (ICs) for multi-beam heterodyne receivers were fabricated. We introduced plasma-enhanced chemical vapor deposition (PE-CVD) for insulator layer deposition and machine-aligned via-hole etching for contact-hole definition on SIS junctions to achieve high uniformity and yield. In the PE-CVD, we applied a compressive/tensile/compressive SiO 2 trilayer technique to control the film stress. The SiO 2 trilayer stress was stable and negligibly low. The uniformity and junction quality yield of the single-pixel prototype SIS mixer ICs were improved in the process applying the PE-CVD and the via-hole etching.

Keywords: sis; sis mixer; uniformity yield; fabrication planar

Journal Title: Journal of Low Temperature Physics
Year Published: 2020

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