LAUSR

Multi-core hardware integrates multiple processing cores onto a single chip. To reduce costs and to improve performance in the average case, these cores typically share a number of hardware resources, including the interconnect, parts of the memory hierarchy (e.g., caches), and main memory. By contending for these shared hardware resources, tasks executing on one core can potentially interfere with tasks executing on another core, substantially increasing their execution times. Contention for shared hardware resources thus poses a significant challenge in the development of predictable hard real-time systems running on multi-core platforms. Three concepts that are useful in a discussion of the real-time behaviour of multicore systems are Timing Composability, Timing Compositionality, and Timing Predictability. Timing Composability means that the timing properties derived for individual tasks studied separately (i.e., executing alone) still hold after their composition with other tasks, for example when they are run with the other tasks executing on the other cores. Timing Composability is highly valued from an industry perspective as it enables incremental development and verification. Different teams can develop and verify different sub-systems, in the knowledge that their timing behaviour will not change when integrated into the complete system. Timing Compositionality means that the timing properties of interest, for example the Worst-Case Execution Time (WCET) of a task can be determined via a decomposition into constituent parts (for example, the worst-case processing time plus the worst-case delays waiting for the bus plus the worse-case latencies waiting for memory). Timing Compositionality is a key property required by much of the research on timing analysis and on integrated timing and schedulability analysis for multi-core platforms, and indeed by WCET analysis in general. Systems that are not timing compositional exhibit timing anomalies meaning that the (local) worst-case behaviour of some resource does not lead to the overall (global) worst-case execution time. Systems with timing anomalies are much