LAUSR

Error concealment (EC) can recover visual quality, while transmission error occurs on video bitstream. Generally, EC is an extra function integrated into the video decoder and also consumes an additional hardware resource. It’s hardware architecture is only activated, when transmission error occurs. Otherwise, it is totally idle, causing a poor hardware utilization. To overcome this problem, the MC-Reused SEC algorithm is proposed. It makes the arithmetic operations of EC compliant with those of MC. This indicates arithmetic operations can be shared with each other. Both MC and EC can be processed on an identical hardware architecture instead of individual ones. Consequently, the limitation on hardware utilization for joint MC and EC can be eliminated. This work has proposed a hardware architecture that can be fully-shared between MC and EC with a 100 % hardware utilization. This hardware architecture can demonstrate a higher hardware efficiency, which considers power, gate count, and throughput. Moreover, the hardware-sharing can also increase the cost-efficiency especially for more advanced process technologies. This work is realized with the technology of TSMC 0.18um CMOS process. The throughputs of MC and EC are 1.0 Gpixels/sec and 320 Mpixels/sec, respectively. Experiment results reveal that this work demonstrates a competitive performance on hardware-efficiency.