With the continuously scaling down of semiconductor technology, the traditional SiO2 as gate dielectric is approaching the physical and electrical limits. Some problems, such as the increasing leakage current and… Click to show full abstract
With the continuously scaling down of semiconductor technology, the traditional SiO2 as gate dielectric is approaching the physical and electrical limits. Some problems, such as the increasing leakage current and reliability issues, seriously affect the transistor performance [1]. HfO2 has been considered to be one of the reasonable alternative solutions due to a suitable dielectric constant (about 25), the relatively large band gap (5.68 eV) and thermal stability with Si substrate [2]. High-k gate dielectric technology has been utilized for CMOS mass production below the 45 nm technology node, however the mainstream of antiradiation CMOS technology is above 65 nm technology node. The study of the radiation effects of high-k gate dielectrics is required before the utilization of 45 nm and below technology nodes for higher integration and capacity ICs aiming at future space applications. But the publications on total ionizing dose (TID) radiation effects of HfO2 or other high-k gate stack materials are very limited, compared with previous relevant researches on SiO2 gate oxide. Furthermore, researchers found the component of radiation-induced interface in HfO2-base device contains two defects: O − 2 and Hf, which is more complex and quite different from that of traditional SiO2-based transistor [3]. So detailed research work is still required before the wide application of this technology in harsh environment. In this article, the effects of Gamma ray radiation and following annealing on HfO2-based MOS capacitors have been investigated. CV hysteresis characteristics were measured at different radiation doses. ∆Vfb (flatband voltage shift) and ∆Vmg (midgap voltage shift) were extracted to calculate ∆Not (oxide trap density variation) and ∆Nit (interface traps density variation). Experiment. Silicon (100) substrate with Ptype doping concentration of 1 × 10 cm was used to fabricate the HKMG MOS capacitors (MOSCAPs). After standard clean process, silicon wafer was treated with buffered oxide etchant (BOE) to remove nature oxide. SiOx was grown on the wafer surface using O3 chemical oxidation. HfO2 high-k dielectric was then deposited onto the SiOx buffer layer by atomic layer deposition (ALD) and treated by post deposition annealing (PDA) using rapid thermal annealing (RTA) at 450C in N2 ambient. TiN/W metal gate was then deposited on the high-k dielectric by ALD and patterned by dry etch using BCl3+SF6 mixed gas. Finally, all samples were metallized with Al(Si) on backside at 380C in N2 ambient for 40 min. High frequency (1 MHz) CV characteristics of the MOS capacitors were measured using Keithley
               
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