LAUSR

The tunnel field effect transistor (TFET) is considered to be a promising alternative device for future low-power VLSI circuits due to its steep subthreshold slope, low leakage current and its efficient performance at low supply voltage. However, the main challenging issue associated with realizing TFET for wide scale applications is its low ON current. To overcome this, a dual gate material with the concept of dielectric engineering has been incorporated into conventional TFET structure to tune the tunneling width at source–channel interface allowing significant flow of carriers. In addition to this, N+ pocket is implanted at source–channel junction of the proposed structure and the effect of strain is added for exploring the performance of the model in nanoscale regime. All these added features upgrade the device characteristics leading to higher ON current, low leakage and low threshold voltage. The present work derives the surface potential, electric field expression and drain current by solving 2D Poisson’s equation at different boundary conditions. A comparative analysis of proposed model with conventional TFET has been done to establish the superiority of the proposed structure. All analytical results have been compared with the results obtained in SILVACO ATLAS device simulator to establish the accuracy of the derived analytical model.