LAUSR

Silicon and sapphire are common substrates for AlN, InGaN, and GaN thin films in several applications such as photovoltaic and light-embedded diodes. Threading dislocations are generated at interfaces between III-nitride (III-N) layers and these substrates because of large lattice and thermal expansion coefficient (TEC) mismatches. These dislocations penetrate the top surface of III-N layers to relax the system by forming V-pit defects. This work presents a thermodynamics-based model to study V-pit formation and growth in InGaN/GaN epilayers on either silicon or sapphire substrates. The model calculates the evolution of V-pit defects in thin films through the energy balance between the strain energy in the III-N layer, dislocation deterioration energy to form new V-pits, and V-pit facet energies that result because of facet formations. The impact of different lattice and TEC mismatches as well as a novel approach, the embedded void approach, on V-pit nucleation and growth is also investigated.