LAUSR

In the recent sub-20 nm technology node, the process variability issues have become a major problem for scaling of MOS devices. We present a design for a strained Si/SiGe FinFET on an insulator using a 3D TCAD simulator. The impact of metal gate work function variability (WFV) on electrical parameters is studied. Such impact of WFV for different mole fractions (x) of the SiGe layer in a strained SOI-FinFET with varying grain size is presented. The results show that as the mole fraction is increased, the variability in threshold voltage (σV T ) and off current (σI off ) is decreased; while, the variability of on-current (σI on ) is increased. A notable observation is the distribution of electrical parameters approaches a normal distribution for smaller grain sizes.