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In recent low-power electronics industry, Tunnel field-effect transistors (TFETs) have shown the superior performance such as decreased leakage current and lower subthreshold slope ( SS ). Previously available research work… Click to show full abstract
In recent low-power electronics industry, Tunnel field-effect transistors (TFETs) have shown the superior performance such as decreased leakage current and lower subthreshold slope ( SS ). Previously available research work have recognized the fact that the precise evaluation of linearity is critical in short channel devices. The linearity analysis of double gate vertical TFET using hetero-dielectric buried oxide (HDB) for high-frequency applications has been investigated in this paper. The aim of using double gate (DG), HDB and work-function engineering is to improve the linearity performance. This work comprises of the analysis of the linearity figure-of-merits in terms of third-order transconductance ( g m 3 ), VIP 2 , VIP 3 , IMD 3 , IIP 3 and 1-dB compression point.
Journal Title: Silicon
Year Published: 2020
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