LAUSR

The adder is an essential component of data paths, and as a result of the shrinking size of electronic devices, it is becoming more susceptible to manufacturing defects and soft errors. Thus, the design of fault-tolerant adders is crucial to the correct operation of arithmetic circuits. In this paper, we propose different fault-tolerant carry look-ahead adder designs against single-bit soft errors based on double modular redundancy DMR and hybrid fault-tolerant schemes. In DMR-based design, we combine a partial hardware redundancy scheme with a protected C-element to achieve full soft error masking, while in the hybrid design, we employ a partial hardware redundancy combined with a parity prediction scheme to improve fault tolerance capability of the adder while reducing area overhead. We use two different voter circuits for merging the partial hardware redundancy into the carry generation logic and to achieve higher fault masking rate and lower area overhead in comparison with existing approaches. Simulation results show that the proposed design schemes take precedence over other schemes in terms of failure rate, area overhead and delay overhead.