LAUSR

Adders and multipliers are the two important arithmetic units in any form of digital filters. Though the adders and multipliers are the fundamental arithmetic units in digital FIR filters, the multipliers are more responsible for power consumption. In existing fast FIR algorithm based digital filters, the number of multipliers is reduced at the expense of adder circuits. This paper presents an arithmetic optimization of reconfigurable digital FIR filters using fast FIR algorithm and modified carry save addition to reduce the power consumption. The modified carry save addition is incorporated to efficiently combine the partial products of the multiplication process. The mathematical analysis reveals that significant amount of hardware savings can be achieved using the proposed design. The ASIC implementation using TSMC 65 nm technology shows that the proposed methodology occupies less area and consumes less power while comparing with conventional approach.