Photo from wikipedia
Abstract This paper presents a new structure for designing a pipeline analog-to-digital convertor with a speed of 100 MS/s, based on TSMC 0.18 µm CMOS technology. With this structure, we extracted… Click to show full abstract
Abstract This paper presents a new structure for designing a pipeline analog-to-digital convertor with a speed of 100 MS/s, based on TSMC 0.18 µm CMOS technology. With this structure, we extracted primary bits from the input signal directly in the first block and sampling was also conducted in the same time. In this new structure that it used for Analog to Digital Converter (ADC) implementation, the first 3 bits are extracted simultaneously with sampling. The simulation results show that, the signal-to-noise ratio for a 10 MHz input is 54.4 dB and the total power consumption with power supply of 1.8 v is 19.7 mW.
Journal Title: AEU - International Journal of Electronics and Communications
Year Published: 2019
Link to full text (if available)
Share on Social Media: Sign Up to like & get
recommendations!