LAUSR

Abstract DC-offset in the input of the phase-locked loop (PLL) is an emerging problem that causes oscillations in the estimated fundamental grid phase, frequency, and voltage amplitude. The DC-offset rejection in grid synchronization is a difficult task due to its low-frequency nature. This paper proposes a method to remove the DC-offset in the single-phase grid synchronization utilizing delay signal cancellation (DSC) and a variable-length time delay (VLTD) based PLL. The small-signal model, stability analysis, and controller gains selection are discussed. The proposed PLL is compared with other single-phase PLLs in terms of the phase settling time, the phase percent maximum overshoot, and the peak of the estimated frequency, to show its advantages.