LAUSR

Abstract Ceaseless efforts have been made by the electronic companies to increase the density of electronic boards. A new design concept consists of burying active and passive electronic components inside inner layers of a Printed Wiring Board (PWB). However this alternative leads to higher thermal stress due to heat concentration at the core of a temperature-sensitive substrate. In order to help the electronic designers to find the optimum placement of these heating devices, a guideline based on analytical approach model is proposed. This presented work focuses on the steady-state solution of the heat equation, resolved by separation of variables and the use of Fourier's series. The domain is an anisotropic, multi-layer parallelepiped, submitted to uniform heat transfer coefficients on its upper and lower surfaces and assumed adiabatic edges. These assumptions can be employed, with confidence, to valid the predictions of chip temperatures at laboratory conditions. To determine its ability to predict the maximum operating temperature of a set of buried chips, that practical solution is compared to its corresponding numerical model representing all the layers of realistic electronic board. Moreover the need to consider each PWB's layer is debated with the aim to faster the chip temperature evaluation. Thus a layer-selection method is investigated to find the best balance between accuracy and computation time. By using such optimised approach the computation time can be shortened by a factor of 600, compared to a detailed numerical analysis, while keeping a similar accuracy. Further, it could be a practical way to proceed to a smart simplification of the numerical model of PWB substrate for actual equipment.