LAUSR

This study reports on the low interface trap density obtained from MOS capacitors and transistors with 2.5nm EOT using MoS2 flakes in back-gated configuration. Design ideology to measure thin flake structures is explained. CV measurements on MOSCAPs show Si-high-k like behavior with a midgap Dit of 2e12cm2eV1. By using CV measurements, the thickness of the MoS2 layer was also extracted. Display Omitted CV measurements and Dit extraction reported for the first time on sub-12nm thick MoS2 flakes.Two different MOS capacitor structures were studied.From the first one, we report an interface trap density of 2e12cm2eV1.The second one provided the thickness of MoS2 films.From FET measurements, we extract Dit of 6e12cm2eV1 from subthreshold slope.