LAUSR

Abstract To address power limitation issues in dark silicon era for multi-core systems-on-chip and chip multiprocessors, run time task-resource and voltage co-allocation with reconfigurable network-on-chip (NoC) framework for energy efficiency (higher performance/watt) is proposed in this work. Distributed resource managers strategy dynamically reconfigures the voltage/frequency-levels of the NoC links and routers and dynamically power-gates the resources depending on the traffic demands and utilization of the resources. A mapping heuristic, namely MinEnergy, has been proposed to minimize overall chip power and energy hotspots in large-scale NoC. We have formulated the mapping and configuration problem into a linear optimization model for the optimal solution and implemented a state-of-the-art Minimum-Path contiguous mapping for comparisons. Simulations are carried out under real-world benchmarks and platforms to demonstrate the effectiveness and efficiency of the proposed schemes and results show that the energy, power, and performance of the proposed dynamic mapping and configuration solution are significantly better (more than 50%) than those of minimum-path mapping solution, while the energy and power consumption of the proposed solution are more than 90% close to the optimal solution.