LAUSR

Abstract Transistor aging is a major reliability concern in nanoscale digital design, and addressing it during high-level synthesis (HLS) is essential to enhance the lifetime of circuits. Motivated by exploring workload effects on aging, we propose an HLS flow that takes workload into account in binding and scheduling steps. We first construct an aging prediction model using support-vector machines (SVM)-based regression techniques. Then, scheduling is performed by utilizing a priority list, which is created based on aging of operations. By exploiting prediction models, functional unit (FU) binding and port assignment are performed simultaneously with the aim of optimizing aging, along with other objectives, by managing the workload of FUs. The results of the proposed method show that the aging rate of FUs is reduced up to 4.3% and the lifetime is increased by an average of 29.22%, compared to previous methods, while imposing little runtime overhead. Moreover, the proposed method prevents non-uniform (asymmetric) aging among FUs with the same type. The coefficient of variation of the aging rates of FUs with the same type is reduced by up to 91.36%.