LAUSR

Abstract This brief presents a scalable parallel neural adder circuit based on spiking neural P systems along with dendritic delays, dendritic feedback, rules on the synapses and astrocyte-like control to create a compact and highly scalable adder circuit. The proposed neural adder circuit adds multiple signed numbers either with few digits or with large number of digits in parallel employing a reduced number of neurons/synapses with simple and homogeneous spiking rules. The proposed neural adder was implemented in a DE0-Nano board (Altera Cyclone IV FPGA) to validate its performance. The results show that its implementation on a low-area low-cost FPGA requires small amount of circuitry. This potentially allows the development of highly parallel architectures that can be used in advanced applications, such as portable mobile robots, mobile devices, image and vision processing, among others.