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Abstract This article demonstrates a Verilog-based triple frame buffer capable of buffering arbitrary data, such as camera frames, between any two asynchronous processes. The frame buffer modules consume 143 logic… Click to show full abstract
Abstract This article demonstrates a Verilog-based triple frame buffer capable of buffering arbitrary data, such as camera frames, between any two asynchronous processes. The frame buffer modules consume 143 logic elements and use a simple, intuitive design. Herein, we discuss the overall implementation of the design as well as practical uses such as in a small camera, or for use as an educational tool.
Keywords:
frame buffer;
fpga implementation;
triple frame;
buffer fpga
Journal Title: HardwareX
Year Published: 2019
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Journal Title: HardwareX
Year Published: 2019
Link to full text (if available)
Share on Social Media: Sign Up to like & get
recommendations!