LAUSR

Abstract The surface roughness of a gate dielectric layer has a large effect on the electrical performance of a printed OTFT (Organic Thin Film Transistor). In this study, a treatment process called calendering is proposed to improve the electrical performance of a printed OTFT by reducing the surface roughness of the gate dielectric layer. Bottom-gate, bottom-contact structural p-type OTFT samples were fabricated by gravure printing (gate electrode and gate dielectric), inkjet printing (source/drain electrodes), and spin coating (p-type channel). Various calendering process conditions composed of temperature, speed, and nip pressure were applied in the fabrication process. Then the calendering process was optimized using the grey-based Taguchi method. For validation of the proposed method, surface roughness of the gate dielectric layer and electrical performance of the non-calendered and calendered OTFT samples were compared and analyzed. The experimental results show a significant improvement that is a 15.92% decrease in the surface roughness, a 15.46% increase in the on-off ratio, and a 30.50% increase in the field-effect mobility.