LAUSR

Abstract A dual side doping-less (DL) GaAs0.5Sb0·5/In0.53Ga0.47As heterojunction tunnel FET (DDL-HTFET) configuration together with hetero-gate-dielectric material (HfO2/SiO2) has been proposed in this article. Hence, N+-pocket with varying electron concentration has been implemented by changing the length of source-side channel (LSC) beneath the gate. The impact of interface trap charges (ITCs) on the execution of the proposed device has been examined by initiating dual (donor and acceptor) sort of confined charges near the semiconductor/insulator intersection. An assessment has been carried out among proposed HTFET and Si-based devices having similar dimensions with respect to dc, analog/RF, and linearity distortion factors thoroughly in existence of ITCs. ATLAS simulations illustrate that the proposed DDL-HTFET is more protected in terms of performance deviation than its Si-based contenders with various ITCs existing at semiconductor/insulator intersection. Hence, DDL-HTFET model can be a promising candidate for the low-power RF applications and can offer improved linearity and less distortion.