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Abstract A vertical MOS architecture implemented on Si nanowire (NW) array with a scaled Gate-All-Around (14 nm) and symmetrical diffusive S/D contacts is presented with noteworthy demonstrations in both processing (layer… Click to show full abstract
Abstract A vertical MOS architecture implemented on Si nanowire (NW) array with a scaled Gate-All-Around (14 nm) and symmetrical diffusive S/D contacts is presented with noteworthy demonstrations in both processing (layer engineering at nanoscale), and in electrical properties (high electrostatic control, low defect level, multi-Vt platform). Furthermore, the versatility and reliability of this technology is evidenced with a CMOS inverter, providing bright perspectives for ultimate scaling.
Keywords:
around field;
transistors vertical;
sub gate;
effect transistors;
field effect;
gate around
Journal Title: Solid-state Electronics
Year Published: 2017
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Journal Title: Solid-state Electronics
Year Published: 2017
Link to full text (if available)
Share on Social Media: Sign Up to like & get
recommendations!