The inevitable current overshoot which follows forming in filamentary RRAM devices is often perceived as a source of variability that should be minimized. This sentiment has led to efforts to… Click to show full abstract
The inevitable current overshoot which follows forming in filamentary RRAM devices is often perceived as a source of variability that should be minimized. This sentiment has led to efforts to curtail the overshoot by decreasing the parasitic capacitance using highly integrated 1T-1R or 1R-1R device structures. While this is readily achievable in single device test structures, it poses an intricate design constraint for memory array designs. Several papers (Degraeve et al., 2010, 2014; Fantini et al., 2013; Raghavan et al., 2013; Padovani et al., 2015) suggest that there is insufficient current to form stable filaments for small parasitic capacitances and/or low current compliance levels. Thus, the relationship between minimizing overshoot current and improved filament stability is tenuous. In this study, we utilize the forming energy-based understanding of filamentary forming to reveal that the parasitic capacitance should be optimized, rather than minimized for better filament control.
               
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