LAUSR

Abstract This paper reports an investigation of the effects of varying different device parameters on the random-dopant-fluctuation (RDF) induced threshold voltage variability (σVT) in junctionless (JL) InGaAs FinFETs. Such investigation is made by means of a 3D numerical device simulator. Both gate length and fin height scaling are found to increase σVT in InGaAs JL FinFETs, similar to that in Si devices, following “Pelgrom’s law” [1] . On the other hand, although the scaling of either fin width (Wfin) or effective oxide thickness (EOT) of the gate insulator reduces σVT in Si JL devices due to enhanced electrostatic integrity; such scaling is found to deteriorate σVT in InGaAs JL FinFETs. Decrease in the density of state capacitance, also known as quantum capacitance, with Wfin or EOT scaling is found responsible for the deterioration of σVT in InGaAs devices.