LAUSR

Abstract Semiconductor manufacturing has reached sub-10-nm technology nodes, and nanoscale gap filling has become an emergency critical requirement for memory with high density and low power consumption. However, it is limited by the non-conformal deposition of current sputtering techniques, such as physical vapor deposition, despite its high quality, low impurity level, and good composition controlling. Here, we present an excellent void-free gap filling results for sub-10-nm nano-pores, and extend the gap-filling limitation of the conventional sputtering technique by the deposit-etch-deposit (DED) method. Coupled with investigating the DED mechanism via the experimental measurements on the nano-pores with different sizes, results indicate that the overhang is removed and atoms are re-deposited during the etching step, which are critical factors for DED process. DED parameters including deposition, etching, and cycling times are investigated and optimized comprehensively. Furthermore, element uniformity and electrical performance are comparable between DED and conventional sputtering technique and have little difference. These results demonstrate that the DED technique, owing to its flexibility and low-cost application compared to conventional sputtering tools, is a potential nanoscale gap-filling solution for sub-10-nm technology nodes.