LAUSR

With the rapid development of artificial intelligence, parallel image processing is becoming an increasingly important ability of computing hardware. To meet the requirements of various image processing tasks, the basic pixel processing unit contains multiple functional logic gates and a multiplexer, which leads to notable circuit redundancy. The pixel processing unit retains a large optimizing space to solve the area redundancy issues in parallel computing. Here, we demonstrate a pixel processing unit based on a single WSe 2 transistor that has multiple logic functions ( AND and XNOR ) that are electrically switchable. We further integrate these pixel processing units into a low transistor-consumption image processing array, where both image intersection and image comparison tasks can be performed. Owing to the same image processing power, the consumption of transistors in our image processing unit is less than 16% of traditional circuits. Reducing circuit redundancy represents a priority for the scalability of parallel computing hardware. Here, the authors report the realization of pixel processing units consisting of single 2D WSe 2 transistors implementing electrically-switchable logic functions. This strategy enables the fabrication of an image processing array with ~16% transistor consumption compared to traditional circuits.