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Nanoscale surface engineering of a high-k ZrO2/SiO2 gate insulator for a high performance ITZO TFT via plasma-enhanced atomic layer deposition

We investigated a high dielectric constant (k) gate insulator (GI) based on the tandem structure of ZrO2 and SiO2 to optimize a high performance oxide thin-film transistor (TFT). We analyzed… Click to show full abstract

We investigated a high dielectric constant (k) gate insulator (GI) based on the tandem structure of ZrO2 and SiO2 to optimize a high performance oxide thin-film transistor (TFT). We analyzed tandem structures with various SiO2 thicknesses to simultaneously achieve higher ZrO2k values and better SiO2 interfacial properties for the In–Sn–Zn-oxide (ITZO) TFT. The TFT exhibited significantly enhanced operational characteristics at a specific SiO2 thickness compared to the GI structures of only ZrO2 or SiO2. We determined the mechanism involved in this improvement by adapting various chemical analysis methods. The optimized tandem-structured GI achieved device stability under positive-bias-and-temperature stress test conditions. Consequently, we evaluated the GI optimization criteria for the development of high performance TFTs. We determined the optimized tandem structure properties with k value, effective mobility, subthreshold swing, and hysteresis of 17.4, 27.7 cm2 V−1 s−1, 0.17 V dec−1, and 0.11 V, respectively, for 8 nm SiO2 on ZrO2.

Keywords: tft; zro2 sio2; high performance

Journal Title: Journal of Materials Chemistry C
Year Published: 2020

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