LAUSR

Traditional solutions for Ethernet transmission of data acquisition systems (DAQ) are mainly based on software transmission control protocol/internet protocol (TCP/IP) stack while its throughput is relatively low and hard to improve. A hardware TCP/IP stack that can greatly promote the Ethernet throughput for generic DAQ is presented. To reduce the memory overhead of FPGA in DAQ, a shared memory method based on parallel and pipeline operations is proposed so that it can realise multiple protocols with just 2 Kb RAM for receiving and sending respectively. Unlike software system, hardware stack is difficult to realise multiple data source transmission simultaneously since it is realised totally by logic circuits. Therefore, a data manage module is designed specially to manage the internal, software and hardware data and it can enhance the flexibility and practicability remarkably. Functional simulation shows that, under 50 MHz system clock, the maximum throughput is near 800 Mbps. A common Megabit Ethernet controller chip is applied in the board test. The results show that the maximum throughput of the whole system is 82.2 Mbps which is much better than designs based on the same or similar network controllers.