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Time-shifted excess loop delay compensation DAC for 2-T s delay in CT-ΔΣ ADCs

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This Letter proposes a new two-sample excess loop delay compensation in continuous-time delta-sigma modulators using time-shifted differentiated digital-to-analogue converter (DAC). This is done by using the information inherently available but… Click to show full abstract

This Letter proposes a new two-sample excess loop delay compensation in continuous-time delta-sigma modulators using time-shifted differentiated digital-to-analogue converter (DAC). This is done by using the information inherently available but ignored in the conventional methods, and therefore no additional hardware is required. Simulation results and mathematical analysis are provided to verify the effectiveness of the proposed structure.

Keywords: time shifted; loop delay; delay compensation; time; excess loop; delay

Journal Title: Electronics Letters
Year Published: 2017

Link to full text (if available)


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