LAUSR

A new all-digital delay-locked loop (ADDLL) using successive-approximation register (SAR) control scheme is presented. The proposed circuit architecture can effectively perform the per-bit acquisition within one clock cycle. Therefore, the divider for generating internal SAR clocks can be further removed to achieve fast-locking capability. Meanwhile, the harmonic-locking problem that often occurs in a wide range of operating frequencies is also eliminated. The test chip is designed and verified with CMOS 0.18 μm technology. The measured acquisition cycles for all operating frequencies (100–800 MHz) are constant as 11 when a 10-bit digital-controlled delay line is employed. The rms/peak-to-peak jitters at the highest and lowest frequencies are 0.775/5.73 and 1.08/8.27 ps, respectively. The chip core occupies an active area of 0.015 mm2 and consumes 9.4 mW at 800 MHz.