LAUSR

This paper proposes a simple yet effective scheme for NAND Flash memories that employ on‐chip microcontroller units (MCUs) to manage internal array operations. Through minimal hardware overhead, the proposed scheme enables—without mask revision— executing new or updated array operations by leveraging the page buffer data cache instead of the hard‐wired on‐chip read‐only memory (ROM) for MCU instruction memory. While not applicable to ordinary user operations, this approach presents significant advantages across various stages of NAND flash memory development and implementation.