LAUSR

This study deals with the robust velocity controller of a DC motor driven by means of parallel DC/DC buck power converters with equal current distribution, from the perspective of a generalised proportional–integral (GPI)-observers-based active disturbance rejection controller (ADRC). The multivariable system is subject to constant torque load demands and changes in the internal parameters. The linear output feedback controllers actively counteract the exogenous and endogenous disturbances that result from the cascading parallel converter and the DC motor. A rapid prototyping tool is used for synthetising the proposed controller into a field-programmable gate array (FPGA) which is based on Matlab/Simulink and a Xilinx System Generator. The robustness of the proposed ADRC system is analysed. The FPGA-based implementation setup is presented with the purpose of validating the theoretical calculations of the proposed DC motor velocity control.