LAUSR

Due to the limitations of the currently widely used von Neumann architecture-based computing system, research on various devices and circuit systems suitable for logic-in-memory computing applications has been conducted. In this work, the silicon-based floating gate memory cell transistor structure, which has been attracting attention as a memory to replace the dynamic random access memory or NAND Flash technology, was newly recalled, and its applicability to logic-in-memory application was confirmed. This floating gate field effect transistor (FGFET) has the advantage that the compatibility of the existing silicon-based complementary metal–oxide–semiconductor (CMOS) process is far superior to that of logic-in-memory application devices to which materials with new memory characteristics are applied. At the 32 nm technology node, which is the front node to which the planar MOSFET structure is applied, an analysis environment that can simultaneously analyze the device and circuit of the FGFET was established. For a seamless connection between FGFET-based devices and circuit analysis, the compact model of the FGFET was developed, which is applied to logic-in-memory ternary content addressable memory (TCAM) circuit design. It was verified that the two types of logic-in-memory TCAM circuits to which FGFETs are applied are superior to a conventional CMOS FET-based TCAM circuit in the number of devices used (=circuit area) and power/energy efficiency.