LAUSR

ABSTRACT A 12-bit time-interleaved 1.0/2.0 GS/s pipeline analogue–digital converter (ADC) is presented and implemented in 0.18 µm SiGe BiCMOS. Such an ADC consists of two identical channels, each of which can operate at 1 GS/s. The two same channels can be interleaved to achieve 2 GS/s speed. In one-channel ADC, four lanes of pipeline ADCs with 250 MS/s are interleaved to realise 1 GHz conversion. To avoid the timing skew-induced error among the four lanes, a dedicated T/H is adopted in one channel. A clock buffer with low jitter is presented to provide a low-voltage swing clock for the T/H by using SiGe devices. The proposed timing system generates the phases needed accurately. A single reference buffer is employed in one-channel ADC to avoid the gain mismatches among the four lanes. An analogue mux with the proposed switch chooses the mode of interleaving or non-interleaving. A trimming digital–analogue converter is employed to eliminate the gain mismatches between the two channels. The measured SNDR and SFDR for one-channel ADC @ 1 GS/s are 60 and 76 dB with Nyquist input. For the interleaved two channels @ 2 GS/s, SNDR and SFDR can achieve 58 and 61 dB with Nyquist input.