LAUSR

ABSTRACT Carbon nanotube field effect transistors (CNFETs) exhibit great promise and extensions to silicon MOSFET due to their excellent electronic properties and extremely small size. Implementable CNFET circuits have operational characteristics to approach the advantage of using multiple-valued logic (MVL) in voltage mode. In MVL implementation computation for the system will be faster than the binary system with improved density of digital circuits. This paper presents two novel 1-bit inverter-based ternary full adder cells which second design cell uses only 37 CNFET transistors in its structure. These designs have been proposed using a new definition of Majority-not based full adder, and are compared to the other adders based on power consumption, speed and power-delay product (PDP). Proposed designs are evaluated using simulation run on HSPICE with 32 nm CNFET standard technology under various operational conditions, including different supply voltages, output load variation and different operating temperatures. According to simulation results, all proposed ternary full adder designs in compare to the state of the art circuits in literature have been demonstrated up to 81% and 80%, respectively, improvement in power consumption and PDP.